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NXP Semiconductors /LPC18xx /CGU /BASE_CGU_OUT0_CLK

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Interpret as BASE_CGU_OUT0_CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OUTPUT_STAGE_ENABLED)PD 0RESERVED0 (AUTOBLOCKING_DISABLE)AUTOBLOCK 0RESERVED0 (32_KHZ_OSCILLATOR)CLK_SEL0RESERVED

PD=OUTPUT_STAGE_ENABLED, CLK_SEL=32_KHZ_OSCILLATOR, AUTOBLOCK=AUTOBLOCKING_DISABLE

Description

Output stage 25 control register for base clock BASE_CGU_OUT0_CLK

Fields

PD

Output stage power down

0 (OUTPUT_STAGE_ENABLED): Output stage enabled (default)

1 (POWER_DOWN): power-down
RESERVED

Reserved
AUTOBLOCK

Block clock automatically during frequency change

0 (AUTOBLOCKING_DISABLE): Autoblocking disabled

1 (AUTOBLOCKING_ENABLED): Autoblocking enabled
RESERVED

Reserved
CLK_SEL

Clock-source selection.

0 (32_KHZ_OSCILLATOR): 32 kHz oscillator

1 (IRC_DEFAULT): IRC (default)

2 (ENET_RX_CLK): ENET_RX_CLK

3 (ENET_TX_CLK): ENET_TX_CLK

4 (GP_CLKIN): GP_CLKIN

5 (RESERVED): Reserved

6 (CRYSTAL_OSCILLATOR): Crystal oscillator

7 (RESERVED): Reserved

8 (PLL0_FOR_AUDIO): PLL0 (for audio)

9 (PLL1): PLL1

12 (IDIVA): IDIVA

13 (IDIVB): IDIVB

14 (IDIVC): IDIVC

15 (IDIVD): IDIVD

16 (IDIVE): IDIVE
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data